Samsung Electronics America CPU DFT Staff Engineer in Austin, Texas

Position Summary

Samsung is a world leader in Memory, LCD and System LSI technologies. We are currently looking for exceptional software and hardware talent to join our Samsung Austin R & D Center (SARC) in Austin, TX and our Advanced Computing Lab (ACL) in San Jose, CA. SARC was established in Austin, TX in 2010 to be one of Samsung’s strategic investments in high performance low power ARM based device technology. Our CPU design teams develop IP for Samsung mobile products and their Application Processor (AP). Our GPU design teams, located in Austin (SARC) and San Jose (ACL), are developing a custom GPU that will be deployed in Samsung mobile products.

The Senior DFT Engineer at Samsung Semiconductor Austin R&D Center (SARC) will be responsible for DFT design and implementation for high-end microprocessors for premium Samsung Galaxy cell phones and mobile devices. This includes architecting and implementing DFT logic modules, test mode controllers, IO BIST, LBIST, Memory BIST, BIRA, and JTAG features. The DFT engineer is also responsible for working with the Architecture/RTL Globals team to develop test debug mode features for our CPUs. This candidate will help improve our DFT design infrastructure to introduce new features, improve test coverage, tester time, and overall productivity. This position will also generate and validate ATPG and other DFT test patterns which include post silicon debug and production silicon support.

Role and Responsibilities

  • Develop RTL for DFT modules

  • Verify functionality through simulation, debugging and formal equivalence

  • Work with RTL owners to incorporate DFT logic in fuctional blocks

  • Work with custom circuit team to define and implement DFT (Scan & BIST) features on custom arrays

  • RTL-to-netlist generation through synthesis

  • Develop DFT insertion and ATPG flow with on-chip test compression

  • Develop DFT timing constraints for physical implementation

  • Work with physical design team on DFT implementation and signoff

  • Gate-level simulation (GLS) including SDF based GLS and debug

Skills and Qualifications

  • MSEE and 8+ years relevant experience (or equivalent education and experience)

  • 8+ years’ experience working in the DFT area

  • Strong knowledge in all aspects of the DFT domain from concept through design implementation and ATE application.

  • Experience with ATPG modelling and ATPG verification of custom circuit blocks

  • Hands-on experience with the followings and/or other comparable DFT tools:

  • DFT compiler

  • DFT max

  • TetraMAX

  • VCS

  • Good scripting and programming skills in Tcl, perl, and/or Python

  • Good knowledge and experiences on physical design tools and flow

  • Good planning and organizing skills in keeping project and tasks on track

  • Must work well in a team oriented environment and be a good team player

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Samsung Electronics is a global leader in technology, opening new possibilities for people everywhere. Through relentless innovation and discovery, we are transforming the worlds of TVs, smartphones, wearable devices, tablets, digital appliances, and network systems, and the entire semiconductor industry with our memory, system LSI, foundry, and LED solutions. Samsung is also leading in the development of the Internet of Things through, among others, our Smart Home and Digital Health initiatives.

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